1. Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to fabricate a capacitor structure for a dynamic random access memory (DRAM), device.
2. Description of Prior Art
As the density of DRAM cells increase, the horizontal dimensions of individual DRAM devices have to be decreased, thus reducing the area available for the DRAM capacitor structure, and thus resulting in unwanted decreases in capacitor surface area. To compensate for the decrease in capacitor surface area, the DRAM industry has featured capacitor structures with increasing vertical features, thus increasing capacitor surface area, and capacitance. The increased vertical features have been achieved via use of various configurations for stacked capacitor structures, such as cylindrical shaped and crown shaped structures. In addition fin type designs have been added to these stacked capacitor structures to supply additional horizontal surface area for the capacitor structures.
This invention will teach a fabrication procedure for formation of a cylindrical shaped, capacitor structure, featuring the use of horizontal grooves, or fins, extending from the vertical sides of the cylindrical shaped capacitor, supplying the desired additional capacitor surface area. The fin type capacitor structure described in the present invention is defined in a fin type capacitor opening, which in turn is formed using a novel process sequence in which the horizontal grooves or channels, in the vertical sides of a capacitor opening, are formed using isolated regions of a conductive material as a mask to selectively, and isotropically, define these horizontal grooves. Prior art, such as Tseng, in U.S. Pat. No. 5,677,222, also describes methods of forming a fin type, DRAM capacitor structure. However the prior art offered by Tseng entails a complex process sequence in which alternating layers of dielectric layers, each having different etch rates, are subjected to a specific isotropic etch to create the fin type configuration. In contrast the present invention forms the fin type grooves in only in a single insulator layer.
It is an object of this invention to fabricate a cylindrical shaped, capacitor structure for a DRAM device, comprised with fin type features, extending horizontally from the vertical sides of the cylindrical shaped capacitor structure.
It is another object of this invention to form a capacitor opening in a thick insulator layer, to accommodate the fin type, cylindrical shaped capacitor structure, with the capacitor opening formed with horizontal grooves or channels located in the vertical sides of the thick insulator layer.
It is still another object of this invention to use discrete regions of rugged polysilicon, or hemispherical grain (HSG), silicon, deposited on the exposed surfaces of the capacitor opening, as an etch mask to isotropically define the horizontal grooves or channels in the exposed regions of the thick insulator layer.
It is still yet another object of this invention to form a fin type, storage node structure for the fin type, cylindrical shaped capacitor structure, comprised of a continuous amorphous silicon layer located in horizontal grooves in the thick insulator layer, and located overlying discrete regions of rugged polysilicon, or HSG silicon.
In accordance with the present invention a method of fabricating a fin type, cylindrical shaped DRAM capacitor structure, is described. After definition of a storage node contact hole in a first composite insulator layer, a storage node contact plug structure is formed in the storage node contact hole, overlying and contacting a source/drain region of an underlying transfer gate transistor. A capacitor opening is then formed in a second composite insulator layer, comprised of an overlying thin silicon nitride layer, and an underlying thick BPSG layer, exposing the top surface of the storage node contact plug structure. Specific deposition and anneal conditions are next used to form a non-continuous layer of discrete regions of rugged polysilicon, or hemispherical grain (HSG), silicon, on the exposed surfaces of the capacitor opening. The discrete regions of rugged polysilicon or HSG, are then used as an etch mask to allow an isotropic etch procedure to selectively form lateral grooves or channels in unprotected regions of the thick BPSG layer, resulting in a capacitor opening featuring horizontal grooves, or channels, in the sides of the thick BPSG layer, with the grooves or channels extending inwards from the vertical sides of the capacitor opening. An amorphous silicon layer is then deposited, contouring the surfaces of the horizontal grooves, as well as overlying the discrete regions of rugged polysilicon. Removal of the portions of amorphous silicon, and portions of discrete regions of polysilicon, from the top surface of the second composite insulator layer result in a storage node structure, in the capacitor opening, comprised of a continuous amorphous silicon layer, overlying discrete regions of polysilicon, and contouring or coating the surfaces of the horizontal grooves of the capacitor opening. Formation of a capacitor dielectric layer on the underlying amorphous silicon storage node structure is followed by formation of a capacitor top electrode structure, resulting in a fin type, cylindrical shaped capacitor structure, featuring the fin type, storage node structures.
An additional embodiment of this invention entails the formation of hemispherical grain (HSG), silicon, on the amorphous silicon surface of the storage node structure, prior to formation of the overlying capacitor dielectric layer.